|For mathematical models, GeneXproTools 4.0 uses the VHDL
grammar to generate VHDL code from its native Karva code, whereas for Logic
Synthesis problems, GeneXproTools 4.0 uses the basic Boolean All
Gates VHDL grammar.
You can translate not only all the evolved models but also exogenous models introduced through the
Change Seed window
into VHDL. The code can then be copied to the clipboard or saved to disk. This code can be freely distributed in source or binary form.
To translate your mathematical models into VHDL, on the GeneXproTools modeling environment, select the
Model Panel, and then, on the Language list box, select
And to translate your logic circuits into VHDL, on the GeneXproTools modeling environment, select the
Model Panel, and
both VHDL and All Gates on the Language list boxes.